The annealing of ion implanted Ga/As has received much study because of its practical importance for field effect transistor (FET) fabrication. The source, drain an channel of an FET are all generally formed by ion implantation. These implants must then be activated by annealing. In the course of annealing these implants, preferential As evaporation from the surface must be avoided. This is normally done either by providing an arsenic overpressure in a hot wall furnace for an extended time (typically about 20 minutes), or with a deposited encapsulant or proximity cap. By proximity capping is meant placing an additional silicon or Ga/As wafer face to face against the sample being annealed to reduce the arsenic evaporation. For practical reasons, none of these methods are entirely satisfactory in a large scale manufacturing environment. Arsenic furnaces involve long thermal exposure, and use large quantities of arsine. Use of deposited encapsulants (such as Si.sub.3 N.sub.4 or SiO.sub.2) or proximity caps stresses the surface of the Ga/As wafer, and tends to cause cracks. Surface deterioration also increases.